1. Field of the Invention
The present invention relates to a reduction of the signal delay in a semiconductor integrated circuit device and, particularly, to a control circuit for effecting a data writing operation at a high speed in the semiconductor integrated circuit device. More particularly, the present invention relates to a highspeed semiconductor integrated circuit device which adopts at least one of high-speed technologies for speeding up the recovery of data lines and the control of data lines and word lines and for achieving higher speed by arranging buffers and pads for each memory array.
Moreover, the present invention relates to a high-speed decoding circuit for a semiconductor processing system such as a processor or a microcomputer (which will be abbreviated herein to the "micon").
Still further, the present invention relates to a speeded-up semiconductor integrated circuit device, and, more particularly, to a data processor or a data processing system having a semiconductor processing system or a semiconductor memory device.
2. Description of the Related Art
A first technology of the prior art will initially be described.
A static type random access memory (SRAM) of the prior art carries out recovery of data lines in response to a rise of a write enable signal (WEB) fed from the outside.
Here in the semiconductor circuit device (or memory), the term recovery implies restoration (or recovery) of that potential of the data line, which has been fluctuated by the writing operation or the like, to a predetermined value. And, the time period required for the recovery is called the "recovery time".
When the decoder is speeded up so as to speed up the SRAM, the subword lines (SWL) are switched before the data lines are recovered, thereby causing an erroneous writing operation or a delay in the recovery time.
Therefore, the technology for reducing the recovery time to zero is described in Japanese Patent Laid-Open No. 69893/1992.
In this Laid-Open document, there is disclosed a selfwrite system in which the recovery is executed by outputting a pulse signal at a predetermined interval. For this, there is disclosed a semiconductor memory device. In this semiconductor memory device (or the memory chip), a first logic operation is carried out between a write enable signal (WEB) and a chip select signal (CS) to output a first logic signal by one timing control circuit (TC) of the memory device. A second logic operation is carried out between the first logic signal and a data input signal to output a second logic signal by one data input buffer and one write pulse generate circuit. In response to the second logic signal, a pulse signal is generated so that the pulse signal produced by the write pulse generate circuit is distributed to all memory cells.
A second technology of the prior art will now be described.
In this second arrangement, a random access memory (RAM), in which a predecoder is arranged at the central predecoder is distributed to individual memory arrays, as described on pp. 5 of Technical Report of Association of Electronic Information Communication, Vol. 91, No. 66 or in Japanese Patent Laid-Open No. 91895/1988 or 144276/1992.
A third technology of the prior art will now be described.
In order to facilitate connections from the lead lines of the package of a semiconductor memory device to a semiconductor memory circuit unit, this semiconductor memory circuit unit is equipped at its outer peripheral portion with input/output buffers and input/output pads, and wiring lines are arranged from those input/output buffers and pads to the inside of the semiconductor integrated circuit unit to transmit signals.
In the technology of the prior art described above, however, no consideration is taken in case the capacity of the memory is increased, in case the degree of integration of the semiconductor integrated circuit device and the memory cells is enhanced, in case the number of memory cells and memory arrays are increased, in case the area of the semiconductor integrated circuit device is increased, or in case the amount of data to be processes is increased. In other words, since the signal produced at one portion in the semiconductor integrated circuit device is transmitted to all the regions such as the memory array and the memory cells in the semiconductor integrated circuit device, a difference is established in the signal transmissions between the individual regions, thus causing a problem of a signal delay. This problem becomes more serious as the area and the degree of integration are raised to higher levels.
The first technology of the prior art has the following problems.
The first problem is as follows. Since pulse signals (PSG) are produced from WEB, CSB and DIN in one portion of the memory chip and are transmitted into the memory chip, skewing of the pulse signal and deformation (break) of the waveform are caused due the increase in the area of the memory chip so that the timing of the pulse signal is different (to cause the signal delay) locally in the chip. This problem makes the design difficult.
Next, a logic is taken between the pulse signal, after it is produced, and a mat select signal (MS) to produce a write control signal. Moreover, since a common data line (CDL) drive signal is produced in response to that write control signal a timing is deviated between the pulse signal and the mat select signal as the memory capacity and the memory chip area are increased, so that the margin of the pulse width of the pulse signal has to be enlarged. As a result, the difference in the signal widths of the WEB, CSB and DIN signals are decreased to cause a second problem that the effect of the self-write system cannot be sufficiently achieved.
Moreover, the common data line (CDL) is controlled by the pulse signal, but the PMOS or a load connected with the data lines is controlled by the WEB signal so that the control cannot be executed at a precise timing. This raises a third problem that the desired effect of the self-write system cannot be sufficiently achieved.
According to this self-write system of the prior art technology, there arises a fourth problem that common data cannot be written at different addresses by fixing the potentials of the WEB signal and the DIN signal and by switching the address signals only.
In the system for the write control with the pulse signal, therefore, skewing of the pulse signal is caused by the increase of the chip area. If, moreover, a logic operation is performed between the pulse signal and another control signal, the timings of the pulse signal and the control signal become different in the chip so that a pulse signal having a precise pulse width cannot be produced.
According to the second and third technologies of the prior art, if the bit number is increased, for example, the addresses increase to by a power of two relative to the increased bit number. As a result, the number of drive circuits increases in accordance with the increase in the addresses so that the circuit scale is accordingly enlarged. The number of gates to be driven by one logic gate of the predecoder or a first stage logic circuit group is increased to increase a fan-out per logic gate thereby to cause a fifth problem that the load capacity increases.
Moreover, the increase in the number of elements composing one chip makes a complicated logic necessary to invite increases in the logic step number, the logic gate number and the wiring line number thereby to cause-a sixth problem that the chip area increases.